SWDnovel Chapter 55 Landing
Chapter 55 Landing
In mid-May, Blue Bay Communications sent the first batch of embedded hardware platforms for engineering development.
Two silver-gray aluminum alloy chassis, four units in each chassis, eight units in total. Each chassis contains a custom-made signal processing board—a heterogeneous architecture of dual-core DSP and FPGA, which is the core computing platform of the Sky Dome ground terminal.
When Zhang Lei opened the first computer case, his fingers were trembling slightly.
"Brother Cheng, the workmanship of this board is exquisite!" He held the board, examining it from all angles. "It's several levels better than the development boards we use in the lab."
"This was custom-made jointly by Blue Bay Communications and the chip manufacturer." Zuo Cheng took the board and glanced at the silkscreen printing. "The DSP has a 600 MHz clock speed, the FPGA uses a 28-nanometer process, and the on-chip RAM is two megabytes. It matches the parameter model we use for simulation."
He spoke the word "consistency" with great confidence. But three days later he realized he was wrong.
The problem occurred during the first board test.
Fang Ze ported the code of the multi-star pipeline scheduler to the DSP, compiled it successfully, burned it successfully, and started running it—then the system crashed at the seventeenth second.
"Memory overflow." Fang Ze stared at the debugger's output, his brows furrowed. "Insufficient stack space."
Zuo Cheng walked over to him and glanced at the data. In the simulation environment, the scheduler's peak memory usage was 1.6 megabytes, while the DSP's on-chip RAM was 2 megabytes, which should theoretically be enough. However, in actual runtime, the code generated by the compiler was 40% larger than the simulated code in the simulation environment—because the real DSP instruction set is different from the general instruction set used in the simulation, and some operations require more intermediate variables and temporary buffers.
1.6 trillion multiplied by 1.4 trillion equals 2.24 trillion. That's over.
"There will always be a gap between simulation and reality." Zuo Cheng's tone was calm, not surprised. "This is a problem that must be faced during the engineering development phase. Simulation verifies the correctness of the algorithm, but the engineering implementation of the code must be re-optimized for real hardware."
"How can we optimize it? Two megabytes of RAM is a hard limit; we can't change it," Fang Ze asked.
"Modify the code, not the hardware." Zuo Cheng sat down next to Fang Ze and opened the scheduler's source code. "First, perform memory profiling—identify which data structures are taking up the most space. Second, perform data compression—use short integers instead of long integers whenever possible, and reuse buffers instead of allocating new space. Third, slim down the code—manually optimize away redundant instructions generated by the compiler."
These three steps sound simple, but in reality, it's a painstaking task of slicing meat piece by piece.
Zuo Cheng and Fang Ze spent a whole week rewriting the scheduler code from scratch. They didn't change the algorithm—the algorithm didn't need to be changed—but rather modified the implementation of each line of code to make it run as efficiently as possible within the limited memory space.
Seven days later, the system was reinstalled. Peak memory usage was 1.78 MB. It was stable. The system ran for twelve hours without crashing or overflowing, and the scheduler's response time perfectly matched the simulation results.
Fang Ze leaned back in his chair and let out a long sigh. There were two obvious fingerprints on his glasses—he had been pushing up his glasses three times more often than usual this week.
"This kind of work is much more tiring than writing algorithms," he rarely complained.
"Algorithms are creation, engineering optimization is sculpting," Zuo Cheng said. "Two methods of accumulation."
But this is only the first module.
Over the next three weeks, the same problem appeared sequentially in the other three modules. The memory issue was more severe in the adaptive parameter sharing engine—the alignment requirements of the circular buffer on the DSP differed from the simulation environment, resulting in actual memory usage being 30% higher than expected. The problem with the beam co-controller was not memory-related, but timing-related—a slight deviation between the FPGA's clock frequency and the ideal clock in the simulation caused the logic for layered precision switching to occasionally miss a clock cycle, resulting in momentary jitter in beam pointing.
The spectrum sensing front end was actually the smoothest – because the embedded optimization of this module was already done in the architecture design phase. Fixed-pointing, DMA pipeline, candidate cyclic frequency pre-screening, each step was designed for real hardware. After being put on the board, only a few minor modifications to the register configuration were made and it ran smoothly.
"Those three cuts weren't in vain," Liu Wei remarked with emotion.
By the end of June, all four modules had been successfully ported to the board and underwent initial integration testing.
Zuo Cheng updated the progress on the whiteboard. The first milestone, set for August, appears to be achievable on time. However, one crucial step remains to be completed: joint testing between the four modules.
Running each module individually is fine, but when four modules run simultaneously on a single board, share the same memory, and compete for the same bus bandwidth, will new problems arise?
Zuo Cheng knew the answer: Absolutely! There are always more bugs in integration testing than in single-module testing, and they are often more hidden and harder to reproduce. This is an ironclad rule of engineering development.
In early July, he convened an internal meeting to review the joint investigation plan from beginning to end.
"The integration testing will be conducted in three rounds." He drew a timeline on the whiteboard. "Round 1: Dual-module integration testing, pairing modules to test compatibility, expected to take one week. Round 2: Three-module integration testing, focusing on testing resource contention and timing conflicts, expected to take one and a half weeks. Round 3: Full-link integration testing, all four modules plus Dingxin's terminal collaboration interface running together, expected to take two weeks. After all three rounds are completed, the prototype will be delivered in August."
Tang Xu looked at the timeline: "Three rounds of joint debugging plus bug fixes, five weeks at most. Time is very tight."
"So from today onwards, everyone will only do one thing—integration testing." Zuo Cheng's gaze swept over everyone. "Other projects are suspended. LoRa technical support will be handled by Ruilian. My school project will be postponed. Within five weeks, 402 has only one goal: deliver a working prototype by August."
No one objected. The atmosphere in the entire office changed from that moment on—all the task cards for other projects on the whiteboard were moved to the far corner, leaving only the three-round timeline of the joint debugging plan in the center, outlined in bold red.
When Yu Ying called Zuo Cheng that night, he was staring blankly at the debugger in his office.
"Brother, you sound very tired."
"It's alright. The joint debugging has just started, it's quite mentally taxing."
"Do you need my help? I can help you with the algorithm issues related to the spectrum sensing part."
"No need, spectrum sensing is actually the most stable." Zuo Cheng smiled. "The problem lies in hardware compatibility, which you can't help with—unless you can double the size of the DSP's on-chip RAM."
Yu Ying smiled: "I can't help with that. But I can bring you lunch."
"No need to make a special trip—"
"It wasn't intentional. I was going to return some books to the University of Washington library anyway, so it was just on my way."
Zuo Cheng knew that it was three subway stops and a ten-minute walk from Lanxing University to the Huada Library, which wasn't convenient at all. But he didn't point it out.
"Thank you for your help, Kongkong."
"No trouble at all." Yu Ying paused for a moment, then added, "Brother, don't try to tough it out during this integration process. If you encounter any problems you can't handle, remember to ask for help. You're not doing this alone."
"I know."
After hanging up the phone, Zuo Cheng turned back to the screen. The waveforms on the debugger were still running frame by frame, and the DSP's memory usage curve fluctuated like a heartbeat.
Five weeks, just hang in there.
He took a deep breath and continued to stare at the curve.